1. Field of the Invention
The present invention relates to an apparatus for processing packets in a high speed router and a method thereof.
2. Description of the Related Art
Generally, in order to transmit an Internet protocol (IP) packet in an Ethernet, a layer 2 address of the IP packet should be known at final output terminal. In order to detect the layer 2 address of the opponent party, the address resolution protocol (ARP) is used in the Internet protocol version 4 (IPv4), and the neighbor discovery protocol (NDP) is used in the Internet protocol version 6 (IPv6).
Since a control processor driven by a routing protocol in a general router process packet-forwarding, the general router has a simple structure managing a routing table and a layer 2 address by one processor. In a high speed router, however, since each of a control processor, an input processor and an output processor performs its own roll and is driven by different protocols, each of the control processor, the input processor and the output processor has own Information Table. Therefore, it is necessary to perform complicated procedures to synchronize the Information Tables of the control processor, the input processor and the output processor in the high speed router.
FIG. 1 is a block diagram illustrating an internal structure of a high speed router according to the related art.
As shown in FIG. 1, the high speed router includes a control processor 100 and a forward processor 300. The forward processor 300 includes an input processor 310 having an input network processor, an output processor 340 having an output network processor 350 and a switch fabric 330.
The control processor 100 and the forward processor 300 are connected through an Ethernet switch 200 and exchange packets or inter processor communication (IPC) messages each other through the Ethernet switch 200.
Forwarding of input packets is actually performed by the input network processor 320 and output network processor 350 which are included in the input processor 330 and output processor 340 of the forward processor 300.
The input network processor 320 and output network processor 350 in the forward processor 300 are connected each other through the switch fabric 330, and the input processor 310 and the output processor 340 are connected each other through an internal bus such as PCI.
Meanwhile, a router may include a plurality of forward processors 300 according to its capacity.
Hereinafter, a conventional technology for creating a forwarding information table and for forwarding a packet using the forwarding Information Table in the high speed router will be described, briefly.
FIG. 2 is a block diagram illustrating a structure of Information Tables managed by each processor in the high speed router shown in FIG. 1 according to the related art. Since identical constitute elements in FIGS. 1 and 2 have identical or similar functions, the detailed descriptions thereof are omitted.
As shown in FIG. 2, the input processor 310 manages a Prefix Table 311 and a Next-hop Table 312, and the output processor 340 manages a Layer 2 Address Table 341 in the forward processor 300.
In the forward processor 300, the input processor 310 and input network processor 320 share the Prefix Table 311 and the Next-hop Table 312 of the input processor 310. The output network processor 350 and the output processor 340 share the Layer 2 address Table 341 of the output processor 340. Information stored in the Prefix Table 110, the network-hop table 120 and the Layer 2 Address Table 130 in the control processor 100 must be synchronized with information stored in the Prefix Table 311 and the Next-hop Table 312 of the input processor 310 and the Layer 2 Address Table 341 of the output processor 340 in the forward processor 300 to be identical each other.
In the input processor 310 of the forwarding processor 300, the entry of the Prefix Table 311 occupies one table entry for one prefix and is mapped to the Next-hop Table 312 in a multi-to-one manner.
The Next-hop Table 32 is mapped to the Layer 2 Address Table 314 of the output processor 340 in a one to one manner. However, in case of a direct routing where a destination address of a forwarding packet is same to an address of the next-hop, a packet may have a plurality of layer 2 addresses although the packet is included in a same prefix.
Accordingly, one table entry is not allocated to a corresponding prefix in the Prefix Table 311 of the input processor 310 according to the related art. Instead of allocating the one table entry to a prefix, one table entry is allocated to all of host addresses in the Prefix Table 311. For example, in case of 24 prefixes, the number of entries in the Prefix Table 311 maximally increases 256. It causes the number of the entries in the Next-hop Table 312 increased, accordingly. Such an increment of the number of the entries causes a problem of increasing a capacity of a memory in a router.
Also, in a control processor 100 where all information tables for forwarding are converged in one processor, the above described problems are not occurred even in case of the direct routing. It provides a cause that makes the IPC message for synchronizing the routing tables in the control processor 100 and the forward processor 300 complicated.